The present invention relates generally to circuit design and, more particularly, to reduction of bus switching activity.
Current computer processors have a number of input-output (I/O) pins that dissipate a significant amount of energy. Many of the I/O pins are dedicated to interfacing to external memory chips through instruction address and data address buses or a multiplexed bus, which is used for both data and instruction addresses. The amount of energy dissipated from the I/O pins is often significant compared to total chip power consumption.
In accordance with the present invention, techniques for reducing transitions on address buses are provided. According to particular embodiments, these techniques reduce power consumption of electronic devices by reducing switching on address busses.
According to a particular embodiment, a method for reducing transitions on an address bus receives an address for communication to a memory on an address bus. The method computes a first offset between the received address and a first prior address and computes a second offset between the received address and a second prior address. The method selects the first offset in response to the first offset being less than the second offset. The method selects the second offset in response to the first offset not being less than the second offset. The method creates an irredundant codeword based, at least in part, on the selected offset and communicates the codeword on the address bus.
According to another embodiment, a method for reducing transitions on an address bus receives an address for communication to a memory on the address bus. The method associates the received address with a sector head. The method performs an exclusive-or operation between the received address and the prior address stored in the associated sector head. The method communicates the result of the exclusive-or operation on the address bus.
Embodiments of the invention may provide various technical advantages. Certain embodiments provide a number of working zones yet allow a processor to utilize an irredundant design. This irredundant design allows a zone register identifier and an offset to the corresponding zone register to be encoded in a codeword with the same width as the original patterns. Another potential advantage is dynamic updating of zones to improve power efficiency of the computer systems. A further potential advantage is reducing the number of gates.
Other technical advantages of the present invention will be readily apparent to one skilled in the art. Moreover, while specific advantages have been enumerated above, various embodiments of the invention may have none, some or all of these advantages.